Project Background

We were engaged to verify the design of a new 5nm AI inference chip being deployed for cloud infrastructure. The chip would provide inference-as-a-service featuring integrated neural network accelerators.

Challenges Faced

• The design contained over 50 different power domains needing verification.
• We had to maximize verification reuse across multiple cloud chip projects.
• Stimulus required cloud-specific scenarios like variable inference batch sizes.
• Stability and reliability were crucial for a cloud service provider.

Our Solutions

• An automated UVM environment verified power management across domains.
• We developed a cloud inference testbench framework reusable across projects.
• Cloud usage models guided our intelligent stimulus generation.
• We used formal methods to prove stability for critical subsystems.
• Extensive constrained random stress tests validated reliability.

Results

• Our power verification environment reduced regression time by 20%.
• The reusable cloud testbench accelerated verification for future chips.
• Stimulus effectively covered a wide range of cloud-based scenarios.
• Formal analysis eliminated bugs in key interfaces and control logic.
• Stringent random stability tests validated the design prior to tapeout.

This project demonstrated our specialized expertise verifying AI systems for cloud applications, while maximizing reuse across projects. Our methods played a key role in the successful pre-silicon validation.

Project Background

We were engaged to verify the design of a new automotive grade AI accelerator chip being deployed in autonomous vehicles. The chip would handle tasks like sensor fusion and driving decision making.

Challenges Faced

• The design required ISO 26262 compliance for safety and reliability.
• Sensor interfaces like LiDAR, radar, and camera needed verification.
• Modeling the real-time autonomous driving environment was difficult.
• Hardware defects could be life-threatening and required rigorous validation.

Our Solutions

• We followed stringent ISO 26262 documentation, traceability, and requirements processes.
• Sensor interface verification involved real-world traffic scenario simulation.
• We leveraged FPGA prototyping to model ADAS scenarios.
• Extensive fault injection, boundary tests, and formal analysis validated the design.

Results

• Our ISO 26262-compliant verification process achieved full certification.
• Interfaces were validated exhaustively against complex simulated inputs.
• FPGA prototyping enabled effective ADAS scenario testing pre-silicon.
• Comprehensive defect analysis ensured the design met safety targets.
• Post-silicon, the chip performed reliably under rigorous real-world conditions.

This project demonstrated our ability to verify an AI chip design within the strict safety and reliability constraints of the automotive market. Our solutions were critical in validating this life-critical system.

Project Background

We were chosen to verify the design of a new 5nm AI accelerator chip being integrated into next-generation supercomputers. The chip would be used to accelerate complex scientific workloads.

Challenges Faced

• The chip complexity required verifying thousands of compute elements.
• Modeling real-world HPC applications like physics simulations was difficult.
• We needed to validate extreme low precision INT4 operation.
• Meeting project timeline to integrate with the supercomputer build was critical.

Our Solutions

• Constrained random techniques efficiently exercised the massively parallel architecture.
• We developed HPC application microbenchmarks focused on math-intensive algorithms.
• Low precision arithmetic models were integrated into our testbenches.
• Reusable environments and automation maximized verification productivity.
• Regression prioritization ensured completion of critical tests pre-tapeout.

Results

• Our focused stimulus achieved 99% functional coverage of compute resources.
• The microbenchmarks accurately modeled key supercomputing workloads.
• We validated full-chip INT4 performance prior to tapeout.
• Reuse and automation enabled signoff 3 weeks ahead of schedule.
• Post-launch, the chip delivered major performance gains for HPC customers.

This project demonstrated our expertise verifying and optimizing the validation of highly complex HPC-focused AI accelerators. Our techniques were pivotal in the 5nm chip's successful pre-silicon verification and integration.

Project Background

We were tasked to help verify the design of a new 5G smartphone SoC with integrated AI acceleration. The chip would provide substantial improvements to camera, AR, voice assistants, and more.

Challenges Faced

• Verifying complex AI inferencing engines for vision, speech, and language.
• Validating the chip met stringent power and thermal requirements.
• Rigorously testing 5G, WiFi, Bluetooth for high reliability.
• Ensuring smooth Android OS integration.
• Meeting demanding project timeline for yearly phone launch.

Our Solutions

• Created reusable mobile AI testbench components for various apps.
• Power verification environment modeled real-world smartphone use cases.
• Protocol compliance tests fully validated connectivity interfaces.
• Android Virtual Devices validated key driver integration.
• CI automation and test parallelization accelerated verification.

Results

• Our reusable mobile AI environments reduced testbench development by 30%.
• Power and thermal testing fully covered worst-case smartphone scenarios.
• Network interfaces passed all certification test suites prior to tapeout.
• Android functionality and compatibility was excellent post-launch.
• Chip verified ahead of schedule to meet phone release timeline.

This project exemplified our expertise verifying complex mobile SoCs under rigorous power, performance, and reliability constraints. Our methodology was key to timely validation and integration for the successful smartphone release.