Project Background

Our team was engaged to design a new AI inference accelerator for a major cloud services provider. This 7nm chip would provide inference-as-a-service to cloud customers across application domains like computer vision, NLP, and recommendation systems. The accelerator had 384 INT8 cores and integrated HBM2E controllers.

Challenges Faced

• The complex heterogeneous architecture resulted in highly congested placement and routing.
• Multiple clock domains for the different blocks posed timing closure difficulties.
• Power consumption had to be minimized to reduce data center TCO for the cloud provider.
• The chip integrated multiple HBM2E stacks which drove challenging floorplanning.

Our Solutions

• A hierarchical methodology was used dividing the chip into semi-independent blocks.
• Congestion maps guided optimization of logic synthesis and placement to reduce hotspots.
• Multi-voltage power domains, MTCMOS techniques, and clock gating optimized power.
• Progressive STA closure was achieved through ECO fixes guided by timing reports.
• The HBM2E tiles were strategically floorplanned using soft macros to reduce implementation disruption.

Results

• The chip taped out within the 10 month schedule to hit product launch timelines.
• Thermal and power goals were achieved, enabling strong data center economics.
• The accelerator delivered up to 100 TOPS of low latency inference throughput for customers.
• Our advanced physical design skills were critical in implementing this complex 7nm AI chip on schedule.
• The engagement led to expanded business opportunities with the cloud provider.

This case study demonstrated our team's expertise in addressing the unique physical design challenges presented by advanced AI accelerator systems-on-chip at 7nm geometries. Our continued partnership with the customer is fueling innovation in cloud-scale AI infrastructure.

Project Background

We were  brought on to help implement the physical design for a new 5nm AI inference chip for an autonomous vehicle customer. This chip would perform real-time sensor fusion and perception algorithms for self-driving tasks. Key requirements were high throughput, low latency, and automotive-grade reliability.

Challenges Faced

• The advanced 5nm node's complexity exacerbated effects like variation, resistive faults, and NBTI aging.
• Hundreds of unique voltage domains were required to minimize power across operating modes.
• The design integrated multiple external sensors with high-speed SERDES interfaces.
• Automotive-grade reliability mandated compliance to standards like ISO 26262.

Our Solutions

• Rigorous EM/IR, fault simulation, and aging analysis validated reliability.
• A hierarchical approach divided the large chip into separate power domains for P&R.
• SerDes logic was optimized through SI-aware floorplanning and routing techniques.
• We leveraged adaptive voltage scaling, MTCMOS, and multi-mode libraries to optimize power.
• Auto-grade tool flows for safety, security, traceability, and documentation were used.

Results

• The design achieved full ISO 26262 compliance and signoff within the 1-year timeline.
• Post-fabrication, the AI chip demonstrated functional safety across use cases.
• Thermal and power budgets were met, enabling integration into vehicle ADAS systems.
• The SERDES interfaces provided the required data throughput from sensors.
• This automotive project expanded our expertise into a key emerging market.

This case study highlights our team's success in applying physical design techniques to deliver a complex, reliable, and high-performance AI chip design for the automotive industry. Our auto expertise has been instrumental in winning future autonomous vehicle engagements.

Project Background

We were engaged by a supercomputing company to implement a 5nm AI accelerator design optimized for scientific HPC workloads like physics simulations, bioinformatics, and seismic modeling. The chip integrated thousands of low-precision matrix compute engines and HBM3 memory stacks.

Challenges Faced

• The dense compute arrays required extremely complex hierarchical floorplanning and placement at 5nm.
• Meeting frequency targets over 1GHz for the fast matrix units posed timing closure issues.
• Power consumption had to be minimized to reduce supercomputer facility costs.
• Large amounts of HBM3 memory drove challenges integrating the memory controllers.

Our Solutions

• We leveraged progressive divide-and-conquer floorplanning and P&R to simplify the large matrix blocks.
• HBM3 integration was improved through soft macro planning and pin stacking optimizations.
• Advanced clock meshing, useful skew, and incremental STA optimization achieved timing closure.
• Power reduction was achieved using multi-voltage domains, power-aware analysis, and gate-level optimizations.

Results

• Our advanced 5nm expertise allowed taping out the accelerator within the 1-year timeline.
• The HBM3 integration resulted in highly efficient memory throughput.
• The compute engines operated at 1.25GHz, delivering record TFLOPS efficiency.
• Post-silicon, the chip provided the massive speedups needed for HPC breakthroughs.
• This project positioned us a key physical design partner for future supercomputing initiatives.

This case study demonstrates our proven physical design skills in implementing high-complexity, high-performance AI chip architectures for the HPC market. Our expertise was instrumental in the success of their next-generation supercomputer.

Project Background

We were brought on to implement the physical design for a new mobile AI accelerator chip for a leading smartphone vendor. Fabricated on a 5nm process, this chip would provide performant neural network inference in a power-constrained smartphone form factor.

Challenges Faced

• Thermal dissipation was highly challenging given the strict power and size limits.
• Meeting timing closure at 5nm while minimizing power required complex optimization.
• The floorplan arrangement had to account for integration with the mobile SoC architecture.
• High-speed interfaces were needed to connect to imaging sensors and modems.

Our Solutions

• Liquid cooling techniques were explored along with thermal-aware placement and routing.
• Progressive synthesis, incremental STA, and ECO optimizations achieved timing.
• Power reduction was achieved by extensive clock gating and power-aware design.
• The chip was floorplanned and pin-assigned to seamlessly integrate with the mobile SoC.
• High-speed SERDES interfaces were optimized through isolation and SI management.

Results

• Our mobile expertise allowed completing the demanding 5nm physical design on time.
• Thermal simulation validated safe operation within smartphone power and form factor constraints.
• The chip delivered leading-edge AI inference performance per watt.
• Post-launch, the AI accelerator received strong reviews for enabling new camera and AI features.
• This successful chip increased our engagements across their mobile roadmap.

This case study demonstrates our team’s skills in addressing the tough integration and optimization challenges involved in implementing advanced mobile AI. Our partnership with the customer continues to fuel their smartphone AI capabilities.